1. Field of Invention
This invention relates generally to semiconductor memories and specifically to an array architecture for housing non-volatile PMOS floating gate memory cells.
2. Description of Related Art
Flash EEPROM, which combines the advantages of EPROM density and EEPROM erasibility, is becoming increasing popular in the semiconductor memory market. Traditionally, flash EEPROM, as well as EPROM and EEPROM, has been fabricated using NMOS technology due to the superior mobility of electrons over holes. EPROM cells are programmed via electron tunneling and erased using ultraviolet radiation, while EEPROM cells are programmed and erased via electron tunneling.
FIG. 1 illustrates a conventional NMOS flash memory cell 10. A p- substrate 12 has an n+ source 14 and an n+ drain 16 formed therein. A channel 18 extends within substrate 12 between the n+ source 14 and the n+ drain 16. A thin gate dielectric layer 20 separates a polysilicon floating gate 22 from the substrate 12. The gate dielectric 20 may be, for instance, a layer of silicon dioxide (SiO.sub.2) having a thickness of approximately 100 .ANG.. A second dielectric layer 24 separates a control gate 26 from the floating gate 22. Although not illustrated in FIG. 1, a protective insulating layer is typically formed over the Flash EEPROM cell 10, and electrical contacts are made to the n+ source 14, the n+ drain 16, and the control gate 26.
To program the cell 10, approximately 5 volts and 12 volts are applied to the drain 16 and control gate 26, respectively, for a few milliseconds, while the source 14 is held at a low potential, e.g., ground potential. In response thereto, electrons accelerate across the channel 18 and, colliding with electrons and lattice atoms proximate the drain 16, generate hot electrons. The hot electrons are attracted to the high positive voltage on the control gate 26 and are injected into the floating gate 22. The resulting accumulation of negative charge within the floating gate 22 increases the threshold voltage of the cell 10, thereby programming the cell 10.
The cell 10 is erased by floating the drain 16, grounding the control gate 26, and applying approximately 12 volts to the source 14. Electrons within the floating gate 22 tunnel through the gate dielectric 20 and into the source 14, thereby restoring the threshold voltage to its original level and, thus, erasing the cell 10.
To read the cell 10, the source 14 is grounded, the drain 16 is held at approximately between 1 and 2 volts, and the control gate 26 is held at approximately 5 volts. Under these bias conditions, the cell 10 will conduct a channel current only if in an erased state.
Technological improvements have led to the development of a PMOS Flash EEPROM cell, as disclosed in the co-pending and commonly owned U.S. patent application Ser. No. 08/557,589 entitled "PMOS Memory Cell with Hot Electron Injection Programming and Tunneling Erasing," filed on Nov. 14, 1995, issued to Chang on Nov. 11, 1997 as U.S. Pat. No. 5,687,118. FIG. 2 illustrates a PMOS floating gate memory cell 30 of the type disclosed in the Chang patent. The cell 30 is formed in an n- well region 32 of a p- substrate 34. A p+ source 36 and a p+ drain 38 are formed in the n- well region 32. A channel 40 extends within the n- well 32 between the p+ source 36 and the p+ drain 38. A polysilicon floating gate 42 is insulated from the n- well region 32 by a thin tunnel oxide layer 44. Preferably, the oxide layer 44 is approximately between 80-130 .ANG. thick and extends over the entire length of channel 40 and portions of both the p+ source 36 and the p+ drain 38. A control gate 46 is insulated from the floating gate 42 by an insulating layer 48.
In some embodiments, the cell 30 is programmed by applying approximately 6.5 volts to the p+ source 36, pulling the p+ drain 38 to between 0 and 2 volts, and coupling a program voltage which ramps from a first potential to a second potential to the control gate 46. Positively charged holes accelerate across the channel 40 towards the p+ drain 38. These holes collide with electrons and lattice atoms in a drain depletion region 50 proximate the p+ drain 38 and result in impact ionization. High energy electrons generated from the impact ionization are attracted to the ramped voltage on the control gate 46 and are injected into the floating gate 42. The resulting accumulation of negative charge on the floating gate 42 increases the threshold voltage of the cell 30, thereby programming the cell 30. This programming mechanism is known as channel hot electron (CHE) injection.
In other embodiments, the cell 30 is programmed by applying a constant positive potential to the control gate 46 to cause the injection of hot electrons, induced by band-to-band tunneling, into the floating gate 46.
The cell 30 is erased by applying approximately 9 volts to the p+ source 36 and to the n- well 32, pulling the control gate 46 to approximately -9 volts, and floating the p+ drain 38. Electrons within the floating gate 42 tunnel through the gate oxide layer 44 and into the p+ source 36, the p+ drain 38, and the channel 40 of the cell 30, thereby returning the threshold voltage of the cell 30 to its intrinsic level. This erasing technique is known as a channel erase.
The cell 30 is read by applying a supply voltage V.sub.CC to the p+ source 36 and the n- well 32. The control gate 46 is coupled to a potential between ground potential and V.sub.CC, and the p+ drain 38 is coupled to a voltage slightly less than V.sub.CC. Under these bias conditions, the cell 30 conducts a channel current only if in a programmed state, i.e., only if the floating gate 42 is charged. Thus, unlike conventional NMOS memory cells, the PMOS cell 30 does not suffer from read disturb problems.
The PMOS flash cell 30 is advantageous in numerous ways over conventional NMOS memory cells. For a detailed discussion of such advantages, refer to the above-mentioned Chang patent, incorporated herein by reference. Because such PMOS memory cells require different bias conditions during programming, erasing, and reading operations, conventional array architectures designed for NMOS floating gate memory cells are not always suitable for PMOS floating gate memory cells. Accordingly, there exists a need for an array architecture which optimizes the performance of PMOS floating gate memory cells.